I. Field of the Invention
The present invention relates to apparatus for communicating pixel data from Random Access Memory (RAM) memory to a display where the number of bits/pixel may be varied.
II. Description of the Problem
In displaying an image, it is well-known to scan a beam across a Cathode Ray Tube (CRT) screen one picture element after another one row after another. For each picture element (or pixel), there is a corresponding brightness or chrominance.
In an all points addressable (APA) display, the brightness or chrominance is independently programmable. That is, for each pixel, a value corresponding to brightness or chrominance is stored in an APA memory. Any value in the memory may be changed at any time in a conventional manner.
As a scanning beam moves along a display screen, the value corresponding to one pixel after another in succession is retrieved and used to affect the magnitude of the scanning beam. For example, when the beam is at the upper left pixel of the screen, a value in memory which corresponds to the upper left pixel is retrieved, and processed in some way, with a resulting value being applied to the beam as it is positioned over the upper left pixel. As the beam moves to the second pixel in the top row, a value in memory corresponding to that pixel is retrieved from memory and processed, with the resulting value being applied to the beam. The value stored for each successive pixel is sequentially retrieved and processed, so that successive resulting values are applied to the beam to produce the image.
The pixel values are communicated serially to the display in the order the beam scans. Starting in the upper left corner, the beam moves horizontally across the video display. At the end of the scanline, the beam is blanked and reset to the beginning of the next line. This continues until all scanlines are drawn. Using current technology, 1024 pixels across and 1024 scanlines are drawn, for a total of 1,048,576 pixels. As is known in the art, the image may be formed of interleaved fields if desired.
Generally, the image must be refreshed periodically to continuously display an image. In a typical system, the display must be refreshed 60 times per second. That is, every pixel value must be read out of the memory array and sent to a CRT controller--which controls the amplitude of the electron beam--60 times per second.
In order to refresh the entire screen in 1/60th of a second, the pixels are drawn at a rate in excess of 100 Megahertz. The memory array must be capable of providing a new pixel every 10 nanoseconds.
To communicate the pixel values fast enough to satisfy the image refresh requirements, video random access memories (VRAMs) are employed. Like conventional dynamic RAMs (DRAMs), a VRAM includes a random access port. The random access port is used to identify a specific location in memory to which data is to be read or written. For example, a first 9-bit word entering the random access port may identify the horizontal position of a location, while a second 9-bit word identifies the vertical position of the location. The two words form the address for a location in memory.
The VRAM also includes a second, serial port. The purpose of the serial port is to convey data words to the CRT controller for one pixel after another. The serial port has a plurality of outputs for conveying out memory data words of some length.
In the past, a plurality of VRAMs in parallel would provide a collective data word of a bitlength, 2.sup.M. The collective data word would enter a shift register stage which would split the data word into a fixed sequence of smaller words derived from the collective data word. The shift register stage permitted serial access, the kind of access required for an APA display. Output from the serial port is controlled by an independent clock. Every pulse of the serial clock causes the VRAM to present a next data value as output therefrom.
There is, however, a problem with using simple VRAMs in refreshing a display. The serial port of the conventional VRAM is normally inflexible. That is, the number of bits allocated to each pixel is normally fixed. For example, the memory may be configured so that each pixel has 8 bits of memory allocated thereto. This results in a tremendous waste of memory space if the pixels represent binary (black/white) image data or color or graylevel data requiring less than 8 bits/pixel. For binary data, a 1024.times.1024 pixel screen would require 128K of memory. However, if 8 bits are allocated to each pixel, a full megabyte of dedicated bitmap memory is required. Defining the memory to have 8 bits/pixel thus results in 876K of unused memory when the pixels represent binary data. This is illustrated in FIG. 1.
In FIG. 1, eight VRAMs 100 to 114 are shown, each having four outputs. Together the eight VRAMs produce 32 parallel outputs VD0 through VD31. To convert the 32 outputs into successive 8-bit pixel values, eight 4-to-1 shift registers 120 through 134 are illustrated. (It is noted that in the present description the term "through" may be used to indicate a sequence of even-numbered elements where there are no odd-numbered elements therebetween.) The VRAM outputs VD0 through VD31 are shown entering specified inputs to the eight 4-to-1 shift registers 120 through 134. For example, shift register 134 receives as its four inputs: VD0 from VRAM 114; VD8 from VRAM 110; VD16 from VRAM 106; and VD24 from VRAM 102. These four bits are shifted out from shift register 134 in sequence. With each clock pulse, each shift register 120 through 134 is able to shift out a bit; together the eight shift registers can shift out an 8-bit value.
First, a word containing VRAM outputs VD0 through VD7 is conveyed along shift register outputs VIDEO0 through VIDEO7. Then a word containing VRAM outputs VD8 through VD15 is output along VIDEO0 through VIDEO7, and so on. So long as each pixel corresponds to 8-bits, the FIG. 1 structure is adequate. If each pixel is to be represented with a 4-bit word (or 2-bit word or 1-bit word), inefficiency and problems result.
Some problems associated with the FIG. 1 structure are understood with reference to TABLE 1 and TABLE 2. TABLE 1 is a table listing the 32 outputs from the VRAMs (of FIG. 1) and indicating which bit B in which pixel P the output corresponds to in either of four environments: when each pixel has an 8-bit, 4-bit, 2-bit, or 1-bit value.
TABLE 1 ______________________________________ Bit definitions for different bits/pixel Bit B in pixel P Bit number 8 bits/pixel 4 bits/pixel 2 bits/pixel 1 bit/pixel ______________________________________ 31 7 0 3 0 1 0 0 0 30 6 0 2 0 0 0 0 1 29 5 0 1 0 1 1 0 2 28 4 0 0 0 0 1 0 3 27 3 0 3 1 1 2 0 4 26 2 0 2 1 0 2 0 5 25 1 0 1 1 1 3 0 6 24 0 0 0 1 0 3 0 7 23 7 1 3 2 1 4 0 8 22 6 1 2 2 0 4 0 9 21 5 1 1 2 1 5 0 10 20 4 1 0 2 0 5 0 11 19 3 1 3 3 1 6 0 12 18 2 1 2 3 0 6 0 13 17 1 1 1 3 1 7 0 14 16 0 1 0 3 0 7 0 15 15 7 2 3 4 1 8 0 16 14 6 2 2 4 0 8 0 17 13 5 2 1 4 1 9 0 18 12 4 2 0 4 0 9 0 19 11 3 2 3 5 1 10 0 20 10 2 2 2 5 0 10 0 21 9 1 2 1 5 1 11 0 22 8 0 2 0 5 0 11 0 23 7 7 3 3 6 1 12 0 24 6 6 3 2 6 0 12 0 25 5 5 3 1 6 1 13 0 26 4 4 3 0 6 0 13 0 27 3 3 3 3 7 1 14 0 28 2 2 3 2 7 0 14 0 29 1 1 3 1 7 1 15 0 30 0 0 3 0 7 0 15 0 31 ______________________________________
For example, it is noted in TABLE 1, that bit number 20 of a 32-bit memory data word corresponds to (a) the 4th bit of pixel number 1 where there are 8 bits/pixel; (b) the 0th bit in pixel number 2 for 4 bits/pixel; (c) the 0th bit in pixel number 5 for 2 bits/pixel; or (d) the 0th pixel in pixel number 11 for 1 bit/pixel. In the fourth column of TABLE 1, it is observed that, for 1 bit/pixel, each bit B is always the 0th bit with each memory word bit number corresponding to a distinct pixel.
TABLE 2 shows which bit number outputs from the VRAMs make up successive pixel values in a 4 bit/pixel environment.
TABLE 2 ______________________________________ Sequence of 4 bit pixels in 8 bit pixel mode ______________________________________ First pixel Bits 27-24 Second pixel Bits 19-16 Third pixel Bits 11-8 Fourth pixel Bits 3-0 ______________________________________
Referring to TABLE 2 and TABLE 1, it is noted that the sequence of bit numbers shown in TABLE 2 (i.e., 27,26,25,24,19,18 . . . ) corresponds to the sequence of pixels 1, 3, 5, 7 in TABLE 1. This is undesirable for two reasons. First, the memory not required when in the 4 bits/pixel mode--rather than the 8 bits/pixel mode--is not recoverable. The unused memory is arranged in alternate nibbles of the 32 bit word output of the VRAMs. A far more desirable solution would allow the unused half of the memory (a full 512 kilobytes) to be recovered for use as program/data storage or a second page of video. Second, because the pixels are stored in alternate nibbles, the display is more difficult to update for an application program. In this regard, the application program must account for the pixel spacing within the word. Similarly, if the apparatus of FIG. 1 is used for 8-bit pixels and 2-bit pixels, then the unused memory in the 2 bit/pixel mode, namely 768 kilobytes, appears as 6 bits of every byte. The wasted memory is quite substantial.